Instruction-level context switch in SIMD processor

Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodimen...

Full description

Saved in:
Bibliographic Details
Main Authors Jeffrey T Brady, Benjiman L Goodman, Anjana Rajendran, Jeffrey A Lohman, Brian K Reynolds, Terence M. Potter
Format Patent
LanguageEnglish
Published 02.11.2022
Subjects
Online AccessGet full text

Cover

Loading…
Abstract Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodiments, context switch circuitry is configured to atomically: save, for the SIMD group, a program counter and information that indicates whether threads in the SIMD group are active using one or more context switch registers, set all threads to an active state for the SIMD group, and branch to handler code for the SIMD group. In some embodiments, the pipeline circuitry is configured to execute the handler code to save context information for the SIMD group and subsequently execute threads of another thread group. Disclosed techniques may allow instruction-level context switching even when some SIMD threads are non-active.
AbstractList Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodiments, context switch circuitry is configured to atomically: save, for the SIMD group, a program counter and information that indicates whether threads in the SIMD group are active using one or more context switch registers, set all threads to an active state for the SIMD group, and branch to handler code for the SIMD group. In some embodiments, the pipeline circuitry is configured to execute the handler code to save context information for the SIMD group and subsequently execute threads of another thread group. Disclosed techniques may allow instruction-level context switching even when some SIMD threads are non-active.
Author Jeffrey A Lohman
Jeffrey T Brady
Terence M. Potter
Anjana Rajendran
Benjiman L Goodman
Brian K Reynolds
Author_xml – fullname: Jeffrey T Brady
– fullname: Benjiman L Goodman
– fullname: Anjana Rajendran
– fullname: Jeffrey A Lohman
– fullname: Brian K Reynolds
– fullname: Terence M. Potter
BookMark eNrjYmDJy89L5WQw8swrLikqTS7JzM_TzUktS81RSM7PK0mtKFEoLs8sSc5QyMxTCPb0dVEoKMpPTi0uzi_iYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXx7k5GZgZmxoamjsaEVQAAIjos8w
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Physics
ExternalDocumentID GB2606315A
GroupedDBID EVB
ID FETCH-epo_espacenet_GB2606315A3
IEDL.DBID EVB
IngestDate Fri Sep 06 06:06:06 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_GB2606315A3
Notes Application Number: GB20220010558
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221102&DB=EPODOC&CC=GB&NR=2606315A
ParticipantIDs epo_espacenet_GB2606315A
PublicationCentury 2000
PublicationDate 20221102
PublicationDateYYYYMMDD 2022-11-02
PublicationDate_xml – month: 11
  year: 2022
  text: 20221102
  day: 02
PublicationDecade 2020
PublicationYear 2022
RelatedCompanies Apple Inc
RelatedCompanies_xml – name: Apple Inc
Score 3.4377604
Snippet Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute...
SourceID epo
SourceType Open Access Repository
SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title Instruction-level context switch in SIMD processor
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221102&DB=EPODOC&locale=&CC=GB&NR=2606315A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwdV3dT8IwEL8gfr4pSvC7D2ZvjaPbCntYjNsYYDIgioY3sm4jkpixOBL-fa91E194bZPL3TX38WvvrgAPuhkx3uEL2l6kHWoyYVNhJxE1EEvYbRazOJFAMRzxwbv5MrNmNfisemHUnNCNGo6IFhWjva-Vv863l1i-qq0sHsUSl1ZPwdTxtRIdMwlnmOa7Tm8y9see5nlO39VGrw6m7dxoW897sC-TaDllv_fhyp6U_H9ACU7hYIK0svUZ1NKsAcde9e9aA47C8rm7AYeqPjMucLG0weIc2HA79JV-yZofIuvN0cmSYrPEQyDLjLwNQ5_kv00Aq-8LuA96U29AkY35n8TzvlvxazShnq2ytAUk6S6EbSbC0nlicr0TpWm3G3HEAwZiOmFcQmsXlavdW9dwIvWm2uvYDdRRgPQW4-xa3CkV_QB3MIGk
link.rule.ids 230,309,786,891,25594,76904
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwdV3dT4NADG_m_JhvOjXzczwY3ojjgGM8ECMwBjq2RafZG-GAxSWGLbJk_769kzlf9tpLmraXtve7a3sA9x09IdSkM0Wd5aaiE2YpzMoSRUMsYakkJWnGgWI0pMG7_jw1pjX43PTCiDmhazEcET0qRX9fiXi93F5ieaK2snxgcyQtHv2J7ckVOiYczhDZc-zeeOSNXNl17b4jD19tPLZTTTWe9mDfREDIp-z3Phzek7L8n1D8EzgYI69idQq1vGhCw938u9aEo6h67m7CoajPTEskVj5YngEJt0NflS9e8yPxenMMslK5nuMmSPNCegsjT1r-NgEsvs-h7fcmbqCgGPGfxnHf2cirXUC9WBR5C6SsO2OWnjGjQzOddswkz7vdhCIe0BDTMe0SWru4XO1eakMjmESDeBAOX67hmNtQtNqRG6ijMvkt5twVuxPm-gGtlISP
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Instruction-level+context+switch+in+SIMD+processor&rft.inventor=Jeffrey+T+Brady&rft.inventor=Benjiman+L+Goodman&rft.inventor=Anjana+Rajendran&rft.inventor=Jeffrey+A+Lohman&rft.inventor=Brian+K+Reynolds&rft.inventor=Terence+M.+Potter&rft.date=2022-11-02&rft.externalDBID=A&rft.externalDocID=GB2606315A