Parallel lookup in first and second valve stores
A cache 2 can receive addresses from two channels in parallel. The cache has two tag memories. The main tag memory 10 contains tags for all entries in the cache. A micro-tag array 22 is smaller than the main tag array and holds a proper subset of its entries. If two addresses are received simultaneo...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
16.12.2015
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Subjects | |
Online Access | Get full text |
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