Formato de instrucción compatible con vectores y ejecución del mismo

• Main Authors: CHARNEY, Mark, DURAN, Santiago Galan, OULD-AHMED-VALL, Elmoustapha, CAVIN, Robert D, GIRKAR, Milind Baburao, SANS, Roger Espasa, ABEL, James C, WU, Lisa, VALENTINE, Robert C, SAN ADRIAN, Jesus Corbal, SAIR, Suleyman, GROCHOWSKI, Edward Thomas, YOUNT, Charles, TOLL, Bret L, HALL, Jonathan Cannon, BRADFORD, Dennis R, ABRAHAM, Seth, WIEDEMEIER, Jeffrey G, SAMUDRALA, Sridhar, FORSYTH, Andrew Thomas
• Format: Patent
• Language: Spanish
• Published: 12.06.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Un formato de instrucción compatible con vectores y su ejecución. De acuerdo con una realización de la invención, un procesador está configurado para ejecutar un conjunto de instrucciones. El conjunto de instrucciones incluye un formato de instrucción compatible con vectores. El formato de instrucción compatible con vectores tiene una pluralidad de campos que incluyen un campo de operación base, un campo modificador, un campo de operación de aumento y un campo de ancho de elemento de datos, donde el primer formato de instrucción admite diferentes versiones de operaciones base y diferentes operaciones de aumento a través de la colocación de diferentes valores en el campo de operación base, el campo modificador, el campo alfa, el campo beta y el campo de ancho del elemento de datos, y en el que solo uno de los diferentes valores puede colocarse en cada uno de los campos de operación base, el campo modificador, el campo alfa, el campo beta, (Traducción automática con Google Translate, sin valor legal) A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is to execute an instruction set. The instruction set includes a first instruction format, wherein the first instruction format includes a first plurality of templates, wherein the first instruction format has a plurality of fields including a base operation field, a data element width field, and a write mask field, wherein the first instruction format supports, through different values in the base operation field, specification of different vector operations, wherein each of the vector operations is to generate a destination vector operand including a plurality of data elements at different data element positions, wherein the first instruction format supports, through different values in the data element width field, specification of different data element widths, wherein the base operation field, the data element width field, and the write mask field may each store only one value on each occurrence of an instruction in the first instruction format in instruction streams. The processor includes a decode unit to decode the occurrences of the instructions in the first plurality of templates, including to: distinguish, for each of the occurrences, which one of the data element widths to use based on a value in the data element width field; and distinguish, for each of the occurrences, the data elements resulting from the occurrence's vector operation to be reflected in the destination vector operand's corresponding data element positions based on the write mask field's content and the data element width for the occurrence. Different values that may be stored in the write mask field distinguish different write mask registers, of a set of write mask registers, that are to store configurable write masks. The data element width for the occurrence distinguishes which of the data element positions of the destination vector operand correspond with which bits of the configurable write masks.