MEMORIA DE SEMICONDUCTOR CON ALTA DENSIDAD DE CELULAS

• Main Author: KENNEY, DONALD M
• Format: Patent
• Language: Spanish
• Published: 01.08.1995
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

SE PROPORCIONA UNA CELULA DE MEMORIA MUY PEQUEÑA QUE UTILIZA SOLO DOS CUADRADOS EN LA SUPERFICIE MAYOR, E INCLUYE, UN SUSTRATO SEMICONDUCTOR (26) CON UNA SUPERFICIE Y UN FOSO (24) DENTRO; UN CONDENSADOR DE CAPACIDAD DE ALMACENAMIENTO (16), CON UN MODO DE ALMACENAMIENTO (20) SITUADO DENTRO DE LA PARED LATERAL DEL FOSO (24); UN INTERRUPTOR (12) ACOPLADO AL CONDENSADOR DE CAPACIDAD (16), CON UN ELEMENTO TRANSPORTADOR DE CORRIENTE (22) DENTRO DE LA PARED LATERAL CITADA, TENIENDO SU DIRECCION LONGITUDINAL, PARALELA AL EJE LONGITUDINAL DEL FOSO (24); UN ELEMENTO DE CONTROL SITUADO EN LA PARED LATERAL DEL FOSO (24), ENTRE EL CONDENSADOR DE CAPACIDAD (16) Y EL ELEMENTO TRANSPORTADOR DE CORRIENTE Y UNA LINEA CONDUCTORA DE ELECTRICIDAD (28) SITUADA EN LA SUPERFICIE MAYOR DEL SUSTRATO SEMICONDUCTOR (26) EN LA DIRECCION ORTOGONAL AL EJE LONGITUDINAL DEL FOSO (24) Y EN CONTACTO CON EL ELEMENTO DE CONTROL (14) DEL INTERRUPTOR (12). ADEMAS, SE FORMARN DOS DELULAS DE MEMORIA COMPLETAS (10A, 10B) EN CADA INTERSECCION DE LINEAS, CON UNA CELULA FORMADA A CADA LADO DEL FOSO (24) EN CADA INTERSECCION. A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, a storage capacitor (16) having a storage node (20) disposed within a given sidewall of the trench (24), a switching device (12) coupled to the storage capacitor (16) and having an elongated current carrying element (22) disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench (24) and a control element (14) disposed on the sidewall of the trench (24) between the storage capacitor (16) and the elongated current carrying element (22), and an electrically conductive line (28) disposed on the major surface of the semiconductor substrate (26) in a direction orthogonal to the longitudinal axis of the trench (24) and in contact with the control element (14) of the switching device (12). Furthermore, two complete memory cells (10A, 10B) are formed at each trench-word line intersection with one cell formed on each side of the trench (24) at each intersection.