3D INDUCTOR DESIGN USING BUNDLE SUBSTRATE VIAS
A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micr...
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| Main Authors | , , |
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| Format | Patent |
| Language | English French German |
| Published |
24.04.2024
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs. |
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| AbstractList | A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs. |
| Author | LAN, Je-Hsiung DUTTA, Ranadeep KIM, Jonghae |
| Author_xml | – fullname: DUTTA, Ranadeep – fullname: KIM, Jonghae – fullname: LAN, Je-Hsiung |
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| DocumentTitleAlternate | 3D-INDUKTORDESIGN MIT BÜNDELSUBSTRATDURCHGÄNGEN CONCEPTION D'INDUCTEUR 3D UTILISANT DES TROUS D'INTERCONNEXION DE SUBSTRAT EN FAISCEAU |
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| Notes | Application Number: EP20220724977 |
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| RelatedCompanies | QUALCOMM INCORPORATED |
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| Snippet | A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a... |
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| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| Title | 3D INDUCTOR DESIGN USING BUNDLE SUBSTRATE VIAS |
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