IMPEDANCE CONTROL IN MERGED STACKED FET AMPLIFIERS

• Main Author: RANTA, Tero Tapio
• Format: Patent
• Language: English; French; German
• Published: 18.01.2023
• Subjects: AMPLIFIERS; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

Apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network (Zg21, ..., Zgn1) coupled to a gate of a cascode FET transistor (M2, ..., Mn) of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the cascode FET transistor (M2, ..., Mn). According to another aspect, a second parallel-connected resistive and inductive network (Zg22, ..., Zgn2) coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first (Zg21, ..., Zgn1) and the second (Zg22, ..., Zgn2) networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output (RFOUT) by the amplifier across stacked FET transistors of the amplifier (M1, M2, ..., Mn).