PROVIDING EXPRESS MEMORY OBSOLESCENCE IN PROCESSOR-BASED DEVICES
Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation re...
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Main Authors | , , , |
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Format | Patent |
Language | English French German |
Published |
12.10.2022
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Subjects | |
Online Access | Get full text |
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Abstract | Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory. |
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AbstractList | Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory. |
Author | SPEIER, Thomas Philip SARTORIUS, Thomas Andrew MCILVAINE, Michael Scott DIEFFENDERFER, James Norris |
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DocumentTitleAlternate | BEREITSTELLEN DER AUSDRÜCKLICHEN VERALTUNG VON SPEICHER IN PROZESSORBASIERTEN VORRICHTUNGEN RÉALISATION DE L'EXPRESSION DE L'OBSOLESCENCE DE MÉMOIRE DANS DES DISPOSITIFS À BASE DE PROCESSEURS |
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Notes | Application Number: EP20200816730 |
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Snippet | Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based... |
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SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
Title | PROVIDING EXPRESS MEMORY OBSOLESCENCE IN PROCESSOR-BASED DEVICES |
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