RELAXATION OSCILLATOR WITH AN AGING EFFECT REDUCTION TECHNIQUE
A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (Ml, M2, M3, M4) and a plurality of controllable switches (SW11, ..., SW8, SW111,...
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Main Author | |
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Format | Patent |
Language | English French German |
Published |
29.05.2019
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Subjects | |
Online Access | Get full text |
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Summary: | A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (Ml, M2, M3, M4) and a plurality of controllable switches (SW11, ..., SW8, SW111, ..., SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current mirror transistors achieves a decrease of frequency degradation caused by aging effect. |
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Bibliography: | Application Number: EP20170204038 |