SEPARATE LINK AND ARRAY ERROR CORRECTION IN A MEMORY SYSTEM

A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include m...

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Bibliographic Details
Main Authors WEST, David Ian, SUH, Jungwon
Format Patent
LanguageEnglish
French
German
Published 23.10.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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