SEPARATE LINK AND ARRAY ERROR CORRECTION IN A MEMORY SYSTEM
A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include m...
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| Main Authors | , |
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| Format | Patent |
| Language | English French German |
| Published |
23.10.2019
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array. |
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| AbstractList | A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array. |
| Author | WEST, David Ian SUH, Jungwon |
| Author_xml | – fullname: WEST, David Ian – fullname: SUH, Jungwon |
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| DocumentTitleAlternate | CORRECTION D'ERREUR DE MATRICE ET DE LIAISON DISTINCTE DANS UN SYSTÈME DE MÉMOIRE SEPARATE VERBINDUNGS- UND ARRAY-FEHLERKORREKTUR IN EINEM SPEICHERSYSTEM |
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| Notes | Application Number: EP20160779289 |
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| PublicationDateYYYYMMDD | 2019-10-23 |
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| PublicationYear | 2019 |
| RelatedCompanies | Qualcomm Incorporated |
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| Snippet | A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a... |
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| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | SEPARATE LINK AND ARRAY ERROR CORRECTION IN A MEMORY SYSTEM |
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