SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES

• Main Authors: MAKARAM, Raghunandan, SANTONI, Amy L, MCKEEN, Francis X, MORRIS, Brian S, BHATTACHARYYA, Binata, CHRYSOS, George Z, JOHNSON, Simon P
• Format: Patent
• Language: English; French; German
• Published: 21.07.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.