VERTICAL TRENCH ROUTING IN A SUBSTRATE

• Main Authors: YONG, Khang Choong, CHEAH, Bok Eng, KONG, Jackson, CHEN, Kuan-Yu, HECK, Howard L
• Format: Patent
• Language: English; French; German
• Published: 25.08.2021
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE; SEMICONDUCTOR DEVICES; WAVEGUIDES

An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.