SYSTEMS AND METHODS FOR CHIP TO CHIP COMMUNICATION

Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a...

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Bibliographic Details
Main Authors ARCUDIA, Kenneth Luis, THURSTON, Jason Alan
Format Patent
LanguageEnglish
French
German
Published 25.12.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.
Bibliography:Application Number: EP20150750168