PARTIALLY BIASED ISOLATION IN SEMICONDUCTOR DEVICES

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltag...

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Bibliographic Details
Main Authors Blomberg, Daniel, Lin, Xin, Zhang, Zhihong, Zuo, Jiangkai, Yang, Hongning, Cheng, Xu
Format Patent
LanguageEnglish
French
German
Published 12.02.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
Bibliography:Application Number: EP20160187929