Fault resistant flip-flop

A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arrang...

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Main Authors SHARMA, VIBHU, MALZAHN, RALF
Format Patent
LanguageEnglish
French
German
Published 30.03.2016
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Abstract A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.
AbstractList A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.
Author MALZAHN, RALF
SHARMA, VIBHU
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DocumentTitleAlternate Bascule résistant aux défaillances
Fehlerresistentes Flipflop
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Snippet A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic...
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SourceType Open Access Repository
SubjectTerms BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Title Fault resistant flip-flop
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