MANAGED INSTRUCTION CACHE PREFETCHING

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common...

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Main Authors LUPON, MARC, KOTSELIDIS, CHRISTOS E, GIBERT CODINA, ENRIC, LATORRE, FERNANDO, MAGKLIS, GRIGORIOS, PAVLOU, DEMOS, MARTINEZ VICENTE, ALEJANDRO, LOPEZ, PEDRO, MARCUELLO, PEDRO, GONZALEZ, ANTONIO, XEKALAKIS, POLYCHRONIS, MARTINEZ, RAUL, HYUSEINOVA, MIREM, ORTEGA, DANIEL, CODINA, JOSEP M, GOMEZ REQUENA, CRISPIN, TOURNAVITIS, GEORGIOS, MADRILES, CARLOS, STAVROU, KYRIAKOS A
Format Patent
LanguageEnglish
French
German
Published 15.07.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Bibliography:Application Number: EP20110878987