Phase control circuit

A phase control circuit includes: a variable delay circuit (6) for delaying a clock signal (101); a first flip-flop circuit (2) having a clock input terminal to which the delayed clock signal (101a) is input and a data input terminal to which a data signal (100) is input; a second flip-flop circuit...

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Main Authors TANIMURA, DAISUKE, YAKIHARA, TSUYOSHI, KODAKA, HIROTOSHI, TEZUKA, KENTARO, BUTATSU, KENTARO, UCHIDA, KENJI, MIURA, AKIRA
Format Patent
LanguageEnglish
French
German
Published 08.08.2007
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Abstract A phase control circuit includes: a variable delay circuit (6) for delaying a clock signal (101); a first flip-flop circuit (2) having a clock input terminal to which the delayed clock signal (101a) is input and a data input terminal to which a data signal (100) is input; a second flip-flop circuit (7) having a clock input terminal to which the data signal (100) is input and a data input terminal to which the delayed clock signal (101a) is input; and an integration circuit (50) for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit (7).
AbstractList A phase control circuit includes: a variable delay circuit (6) for delaying a clock signal (101); a first flip-flop circuit (2) having a clock input terminal to which the delayed clock signal (101a) is input and a data input terminal to which a data signal (100) is input; a second flip-flop circuit (7) having a clock input terminal to which the data signal (100) is input and a data input terminal to which the delayed clock signal (101a) is input; and an integration circuit (50) for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit (7).
Author KODAKA, HIROTOSHI
MIURA, AKIRA
TANIMURA, DAISUKE
UCHIDA, KENJI
YAKIHARA, TSUYOSHI
BUTATSU, KENTARO
TEZUKA, KENTARO
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– fullname: TEZUKA, KENTARO
– fullname: BUTATSU, KENTARO
– fullname: UCHIDA, KENJI
– fullname: MIURA, AKIRA
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DocumentTitleAlternate Circuit de commande de phase
Phasenregelschaltung
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Snippet A phase control circuit includes: a variable delay circuit (6) for delaying a clock signal (101); a first flip-flop circuit (2) having a clock input terminal...
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SubjectTerms AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Title Phase control circuit
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