MRAM having semiconductor device integrated therein

A magnetic memory cell (10) has a semiconductor layer (12) positioned between first (11) and second (13) ferromagnetic layers forming either a p-n or Schottky junction. A antimagnetic layer (34) is positioned between the second ferromagnetic layer and a digit line (35) for pinning a magnetic vector...

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Bibliographic Details
Main Authors SHI, JING, TEHRANI, SAIED
Format Patent
LanguageEnglish
French
German
Published 17.08.2005
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A magnetic memory cell (10) has a semiconductor layer (12) positioned between first (11) and second (13) ferromagnetic layers forming either a p-n or Schottky junction. A antimagnetic layer (34) is positioned between the second ferromagnetic layer and a digit line (35) for pinning a magnetic vector within the second ferromagnetic layer. In a second embodiment, a gate contact (37) is spaced apart from the layer of semiconductor material for controlling the electron flow through the semiconductor layer.
Bibliography:Application Number: EP20000127096