DESIGN RULE CHECKING SYSTEM AND METHOD

• Main Authors: PATI, YAGYENSH, C, WANG, YAO-TING, CHANG, FANGNG
• Format: Patent
• Language: English; French; German
• Published: 02.08.2000
• Edition: 7
• Subjects: APPARATUS SPECIALLY ADAPTED THEREFOR; BASIC ELECTRIC ELEMENTS; CALCULATING; CINEMATOGRAPHY; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; ELECTROGRAPHY; HOLOGRAPHY; MATERIALS THEREFOR; ORIGINALS THEREFOR; PHOTOGRAPHY; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES; PHYSICS; SEMICONDUCTOR DEVICES

A method for performing design rule checking on an optical proximity correction (OPC) corrected or otherwise corrected designs is described. The corrected design is accessed to generate a simulated image (2010). The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer was exposed to an illumination source directed through the corrected design (2020). The characteristics of the illuminaiton source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout (2020). Also, the simulated image can be compared with an ideal layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.