Semiconductor device planarization method

• Main Authors: HAMAMOTO, KUZUHIRO, ASHIGAKI, SHIGEO
• Format: Patent
• Language: English; French; German
• Published: 05.01.2000
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A semiconductor manufacturing method for devices, such as a DRAM, having a plurality of circuit elements of at least two substantially different heights (such as memory-cells vs. peripheral circuits) on a common semiconductor substrate. A plurality of circuit elements of at least two substantially different heights are formed on a common semiconductor substrate. A common insulating layer, such as BPSG, whose top surface has substantial variation in height above the substrate, is deposited over the circuit elements. A resist mask layer is deposited over the insulating layer with openings over high portions of the insulating layer's top surface exceeding a first predetermined height. Then the insulating layer's high portions are etched down to a second predetermined height to make its overall top surface more even, and the resist mask layer removed. The enables a working layer that would be easily damaged by substantial height variation to be deposited on the evened insulating layer.