Improvements in or relating to dynamic random access memory devices

A dynamic random access memory device (10) includes three separate sections - an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate...

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Bibliographic Details
Main Authors SHICHIJO HISASHI, TENG, CLARENCE W, CHEN, IHIN
Format Patent
LanguageEnglish
French
German
Published 06.11.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A dynamic random access memory device (10) includes three separate sections - an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).
Bibliography:Application Number: EP19950302940