SELF-ALIGNED SEMICONDUCTOR DEVICES
A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 mu m and lower. In a preferred embodime...
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Main Author | |
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Format | Patent |
Language | English French German |
Published |
14.05.1990
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Edition | 4 |
Subjects | |
Online Access | Get full text |
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