Elektrischer Widerstand in Chip-Bauweise für Oberflächenbestückung und Verfahren zu seiner Herstellung
The electrical resistor in chip form is intended to be soldered in particular onto a printed circuit board or onto a hybrid circuit substrate. It comprises an insulating electrical substrate (1) of the ceramic type, onto which is tied a metal or resistive alloy sheet (3) by an adhesive layer of orga...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | German |
Published |
05.05.1994
|
Edition | 5 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | The electrical resistor in chip form is intended to be soldered in particular onto a printed circuit board or onto a hybrid circuit substrate. It comprises an insulating electrical substrate (1) of the ceramic type, onto which is tied a metal or resistive alloy sheet (3) by an adhesive layer of organic resin (2).
The resin layer (6) leaves free, in the vicinity of two opposite edges of the substrate (1), two end portions (5) of the stamped resistive sheet (3). These two portions (5) of the resistive sheet are each covered by a thin layer (8) of a metal or alloy adhering to the resistive sheet (3), this layer (8) being covered by a second thicker layer (9) of metal or conducting alloy, and this second layer (9) being covered with a third, likewise thicker, layer (14) of a solderable alloy, these three stacked layers (8, 9, 14) also extending over the two opposing lateral faces of the substrate (1) and partially over that face (13) of the substrate opposite the stamped resistive sheet (3).
Use in particular in printed or hybrid circuits. |
---|---|
AbstractList | The electrical resistor in chip form is intended to be soldered in particular onto a printed circuit board or onto a hybrid circuit substrate. It comprises an insulating electrical substrate (1) of the ceramic type, onto which is tied a metal or resistive alloy sheet (3) by an adhesive layer of organic resin (2).
The resin layer (6) leaves free, in the vicinity of two opposite edges of the substrate (1), two end portions (5) of the stamped resistive sheet (3). These two portions (5) of the resistive sheet are each covered by a thin layer (8) of a metal or alloy adhering to the resistive sheet (3), this layer (8) being covered by a second thicker layer (9) of metal or conducting alloy, and this second layer (9) being covered with a third, likewise thicker, layer (14) of a solderable alloy, these three stacked layers (8, 9, 14) also extending over the two opposing lateral faces of the substrate (1) and partially over that face (13) of the substrate opposite the stamped resistive sheet (3).
Use in particular in printed or hybrid circuits. |
Author | COLLINS, FRANKLIN, LEWISTON, NEW YORK, US FLASSAYER, CLAUDE, F-06700 ST LAURENT DU VAR, FR |
Author_xml | – fullname: FLASSAYER, CLAUDE, F-06700 ST LAURENT DU VAR, FR – fullname: COLLINS, FRANKLIN, LEWISTON, NEW YORK, US |
BookMark | eNqNjDsOgkAURafQwt8eJvYkRIOfVsTQ2RAtyQAXmTB5kPnExPW4DDo25pi4AKtb3HPOnE2oI8yYTBRaq6UpG2h-lxW0sYIqLonHjeyDk3BPSANej4Pm1wK6VuPb01TA2HEoW0cP7rxx85doNIi_HDeQ5IPpNwelPLNk01oog9VvF2x9SbI4DdB3OUwvShBsfk52xzCM9ocoyzbbv6APhoNFvg |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
Edition | 5 |
ExternalDocumentID | DE69005785TT2 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_DE69005785TT23 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 14:32:07 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | German |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_DE69005785TT23 |
Notes | Application Number: DE19906005785T |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940505&DB=EPODOC&CC=DE&NR=69005785T2 |
ParticipantIDs | epo_espacenet_DE69005785TT2 |
PublicationCentury | 1900 |
PublicationDate | 19940505 |
PublicationDateYYYYMMDD | 1994-05-05 |
PublicationDate_xml | – month: 05 year: 1994 text: 19940505 day: 05 |
PublicationDecade | 1990 |
PublicationYear | 1994 |
RelatedCompanies | SFERNICE SOCIETE FRANCAISE DE L'ELECTRO-RESISTANCE, PARIS, FR |
RelatedCompanies_xml | – name: SFERNICE SOCIETE FRANCAISE DE L'ELECTRO-RESISTANCE, PARIS, FR |
Score | 2.4275167 |
Snippet | The electrical resistor in chip form is intended to be soldered in particular onto a printed circuit board or onto a hybrid circuit substrate. It comprises an... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRICITY RESISTORS |
Title | Elektrischer Widerstand in Chip-Bauweise für Oberflächenbestückung und Verfahren zu seiner Herstellung |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940505&DB=EPODOC&locale=&CC=DE&NR=69005785T2 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NS8NAEB1KFfWmVVGrsojkFoxNNu0lCE1SitAPJNbeSraZYNqQliah4O_xZ_TWP-ZsbKunQg4hkwzJwNuZ7M57C_CIJiU9nQeqFghTNTjnqh_WA9XExrMu9JAyviQKd7pm-914HfJhCSZbLkyhE7osxBEJUWPCe1aM1_O_SSyn6K1Mn0REl2YvLc9ylGBDFzPkxmyK07Tcfs_p2YptW46rdN8s-gnUpK6LR8P1gSyjpc6-O2hKVsr8f0ppncJhn7wl2RmUAqzAsb3dea0CR53NgjedbrCXnkPkxjjNCJMyzOwj2pJSWJQw-zOaq00_X2KUIgvXqwXrCVyE8fp7XPRwpdl6NZ4SsFlOTwzI5Ms-O_aVsxQl_4-1pTuMY7rnAh5arme3VXrn0S5AI8fdfZ5X0y-hnMwSvAImhK75fiPUeV0Ysuky4PWaQA0F1dVUGlxDdY-jm73WKpz8ygpzOm6hnC1yvKP8nIn7IrA_YJSY-w |
link.rule.ids | 230,309,786,891,25594,76906 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NT4NAEJ00aqw3rRq1fmyM4UbEwkIvxKRAg9qvGKy9NWxZIpbQpkCa-Hv8Gb31jzmLbfXUhANhYAKTvJ1hd95bgDuuY9JTaSArAdNljVIq-6ERyDqvP6hMDTHjC6Jwu6O7b9rzgA5K8LnmwhQ6ofNCHBERNUK8Z8V4Pf2bxLKL3sr0nkV4afLY9ExbClZ0MU1szCbZDdPpde2uJVmWaTtS59XEn0BF6Lp4OFzvGkKdV5RO_YZgpUz_p5TmIez10FuSHUEp4BUoW-ud1yqw314teOPpCnvpMUROzMcZYlKEmbxHa1IKiRJifURTueHncx6lnITLxYx0GZ-F8fJ7VPRwpdlyMRojsEmOT_TR5Is-O_KVk5QL_h9xhTsex3jPCdw2Hc9yZXzn4SZAQ9vZfJ5XU09hJ5kk_AwIY6ri-_VQpQbTRNNlQI0a4wpnWFdjaXAO1S2OLrZab6Dseu3WsPXUeanCwa_EMMXjEnayWc6vMFdn7LoI8g-xFZvo |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Elektrischer+Widerstand+in+Chip-Bauweise+f%C3%BCr+Oberfl%C3%A4chenbest%C3%BCckung+und+Verfahren+zu+seiner+Herstellung&rft.inventor=FLASSAYER%2C+CLAUDE%2C+F-06700+ST+LAURENT+DU+VAR%2C+FR&rft.inventor=COLLINS%2C+FRANKLIN%2C+LEWISTON%2C+NEW+YORK%2C+US&rft.date=1994-05-05&rft.externalDBID=T2&rft.externalDocID=DE69005785TT2 |