DE2330651
The asynchronous signal is complemented and directed to a latching logic circuit as the data input and the synchronous signal are directed to the clock input of the latching circuit. The latching circuit has built-in delays to reliably latch if the low or active portion of the asynchronous pulse occ...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
13.01.1983
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Subjects | |
Online Access | Get full text |
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Summary: | The asynchronous signal is complemented and directed to a latching logic circuit as the data input and the synchronous signal are directed to the clock input of the latching circuit. The latching circuit has built-in delays to reliably latch if the low or active portion of the asynchronous pulse occurs during the "window" or high portion of the synchronous signal. The latching circuit also includes a jamming circuit connected to its clock input whereby a low or disabled window time of the synchronous signal prevents a change in state by the latching circuit. A pulse delay circuit generates a sampling pulse a period of time after the window time to sample the output of the latching circuit. |
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Bibliography: | Application Number: DE19732330651 |