Verfahren und Einrichtung zum Einplanen und Abfertigen von Befehlen in einer Prozessor-Pipeline

A method of scheduling instructions in a computer processor. The method comprises fetching instructions to create an in-order instruction buffer, and scheduling instruction from the instruction buffer into instruction slots within instruction vectors in an instruction vector table. Instruction vecto...

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Bibliographic Details
Main Author SHEAFFER, GAD S
Format Patent
LanguageGerman
Published 12.04.2007
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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