Protection against electrostatic discharge for integrated circuit in semiconductor substrate
Vertically to the surface (10) of the semiconductor substrate (30) is located in aa surface region (52) a transistor diode (44,56,40,50,52,54). When the diodee is poled in blocking direction, a punch through can take place at the coupling structure (540,46) prior to breakdown between surface region...
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Main Authors | , |
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Format | Patent |
Language | English German |
Published |
13.12.2001
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | Vertically to the surface (10) of the semiconductor substrate (30) is located in aa surface region (52) a transistor diode (44,56,40,50,52,54). When the diodee is poled in blocking direction, a punch through can take place at the coupling structure (540,46) prior to breakdown between surface region and base-emitter structure (44,56,40,50.Between the bore-emitter structure and the coupling structure is fitted a region (500), whose doping type is opposite to that of the surface region. Between the region (500) and the base-emitter structure is a low-ohmic connection (510), thus forming a lateral diode between the region and surrounding surface for eneregising the vertical transistor diode.
Es wird eine ESD-Schutzvorrichtung vorgeschlagen, die einen vertikalen als Diode geschalteten Bipolar-Transistor umfaßt, der ein zusätzliches ausgelagertes Basisgebiet aufweist. Die erfindungsgemäße Anordnung weist bei platzsparendem Aufbau eine gegenüber bekannten Anordnungen verringerte Differenz zwischen Haltespannung und Durchbruchspannung auf. |
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Bibliography: | Application Number: DE2000128008 |