Semiconductor structure and test system
The utility model discloses a semiconductor structure and a test system. The semiconductor structure includes: a substrate; the doped layer is formed on the first surface of the substrate; and a plurality of trenches, each groove penetrates through the doped layer and extends into the substrate; whe...
Saved in:
Main Authors | , , , , , , |
---|---|
Format | Patent |
Language | Chinese English |
Published |
24.09.2019
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | The utility model discloses a semiconductor structure and a test system. The semiconductor structure includes: a substrate; the doped layer is formed on the first surface of the substrate; and a plurality of trenches, each groove penetrates through the doped layer and extends into the substrate; wherein the plurality of grooves comprise at least one first groove and at least one second groove, each second groove is used for forming a grid electrode of the corresponding semiconductor device, and each first groove defines and isolates the test region with a closed-loop boundary in the doped layer. According to the semiconductor structure, the test region is formed while the semiconductor device is formed, and the test region comprises the doped layer and the first groove penetrating through the doped layer, so that the doped layer has a clear boundary, key parameters such as body region resistance of the semiconductor device can be more accurately represented, and the yield and reliability of products are impro |
---|---|
AbstractList | The utility model discloses a semiconductor structure and a test system. The semiconductor structure includes: a substrate; the doped layer is formed on the first surface of the substrate; and a plurality of trenches, each groove penetrates through the doped layer and extends into the substrate; wherein the plurality of grooves comprise at least one first groove and at least one second groove, each second groove is used for forming a grid electrode of the corresponding semiconductor device, and each first groove defines and isolates the test region with a closed-loop boundary in the doped layer. According to the semiconductor structure, the test region is formed while the semiconductor device is formed, and the test region comprises the doped layer and the first groove penetrating through the doped layer, so that the doped layer has a clear boundary, key parameters such as body region resistance of the semiconductor device can be more accurately represented, and the yield and reliability of products are impro |
Author | LI JINGYI ZHANG XIAOLIN ZHANG ZHIWEN ZHU LINDI PEI ZIWEI ZHOU YUAN WANG CHAO |
Author_xml | – fullname: LI JINGYI – fullname: ZHOU YUAN – fullname: ZHANG XIAOLIN – fullname: ZHU LINDI – fullname: ZHANG ZHIWEN – fullname: WANG CHAO – fullname: PEI ZIWEI |
BookMark | eNrjYmDJy89L5WRQD07NzUzOz0spTS7JL1IoLikCMkqLUhUS81IUSlKLSxSKK4tLUnN5GFjTEnOKU3mhNDeDkptriLOHbmpBfnxqcUFicmpeakm8s5-RgaWJsYmhiWVoqDFRigAgdSsQ |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | 半导体结构及测试系统 |
ExternalDocumentID | CN209434149UU |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_CN209434149UU3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 16:14:12 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | Chinese English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_CN209434149UU3 |
Notes | Application Number: CN201821898448U |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=CN&NR=209434149U |
ParticipantIDs | epo_espacenet_CN209434149UU |
PublicationCentury | 2000 |
PublicationDate | 20190924 |
PublicationDateYYYYMMDD | 2019-09-24 |
PublicationDate_xml | – month: 09 year: 2019 text: 20190924 day: 24 |
PublicationDecade | 2010 |
PublicationYear | 2019 |
RelatedCompanies | BEIJING YANDONG MICROELECTRONICS TECHNOLOGY CO., LTD |
RelatedCompanies_xml | – name: BEIJING YANDONG MICROELECTRONICS TECHNOLOGY CO., LTD |
Score | 3.3512988 |
Snippet | The utility model discloses a semiconductor structure and a test system. The semiconductor structure includes: a substrate; the doped layer is formed on the... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | Semiconductor structure and test system |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&locale=&CC=CN&NR=209434149U |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQsbAwSbJITjbRTTGxSNMFlpIWukmGxqm6SeapwNg2sExJA28S8_Uz8wg18YowjWBiyILthQGfE1oOPhwRmKOSgfm9BFxeFyAGsVzAayuL9ZMygUL59m4hti5q0N4xsHYD9ifUXJxsXQP8Xfyd1ZydbZ391PyCgHKgg9CA3YFQZgZWUDMadM6-a5gTaFdKAXKV4ibIwBYANC2vRIiBqSpDmIHTGXbzmjADhy90whvIhOa9YhEG9WDQOvb8PNABrflFCpCDX0uLUhUS81IUgA3GEgXIqcyiDEpuriHOHrpAG-Ph3ot39kM4LtRYjIEF2O9PlWBQALaFzJITTYGlQIqFCbBcSkwzSjYxTDZINDMDZiqzJEkGaTwGSeGVlWbgAoWWLnh6RYaBBejkVFlg7VqSJAcOFgAzJn4X |
link.rule.ids | 230,309,786,891,25594,76903 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQsbAwSbJITjbRTTGxSNMFlpIWukmGxqm6SeapwNg2sExJA28S8_Uz8wg18YowjWBiyILthQGfE1oOPhwRmKOSgfm9BFxeFyAGsVzAayuL9ZMygUL59m4hti5q0N4xsHYD9ifUXJxsXQP8Xfyd1ZydbZ391PyCgHKgg9CA3YFQZgZWc2CXENxVCnMC7UopQK5S3AQZ2AKApuWVCDEwVWUIM3A6w25eE2bg8IVOeAOZ0LxXLMKgHgxax56fBzqgNb9IAXLwa2lRqkJiXooCsMFYogA5lVmUQcnNNcTZQxdoYzzce_HOfgjHhRqLMbAA-_2pEgwKwLaQWXKiKbAUSLEwAZZLiWlGySaGyQaJZmbATGWWJMkgjccgKbyy8gycHiG-PvE-nn7e0gxcoJDTBU-1yDCwAJ2fKgusaUuS5MBBBAA87IEB |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Semiconductor+structure+and+test+system&rft.inventor=LI+JINGYI&rft.inventor=ZHOU+YUAN&rft.inventor=ZHANG+XIAOLIN&rft.inventor=ZHU+LINDI&rft.inventor=ZHANG+ZHIWEN&rft.inventor=WANG+CHAO&rft.inventor=PEI+ZIWEI&rft.date=2019-09-24&rft.externalDBID=U&rft.externalDocID=CN209434149UU |