Clock tree unit, clock network structure and FPGA clock structure

The utility model relates to a clock tree unit, clock network structure and FPGA clock structure, wherein clock tree unit includes: horizontal drive module, a plurality of vertical interface module, aplurality of programmable logic unit, be provided with the drive of horizontal branch in the program...

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Bibliographic Details
Main Authors CHENG XIANZHI, WEI QIN, CHEN WEIXIN, JIA HONG, FENG XIAOLING, LIU JING
Format Patent
LanguageChinese
English
Published 03.07.2018
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:The utility model relates to a clock tree unit, clock network structure and FPGA clock structure, wherein clock tree unit includes: horizontal drive module, a plurality of vertical interface module, aplurality of programmable logic unit, be provided with the drive of horizontal branch in the programmable logic unit, the horizontal drive module, the electricity is connected to a plurality ofly vertical interface module, vertical interface module, with the drive of horizontal branch corresponds to be connected, the drive of horizontal branch is used for making treat that transmission signal isa plurality of transmit between the programmable logic unit. The utility model discloses technical scheme is through setting up the drive of horizontal branch in the programmable logic unit for the programmable logic unit is followed vertical interface module received and is treated that transmission signal can transmit each other, and the overall transmission signal of treating is sent to the programmable logic unit to th
Bibliography:Application Number: CN201721678716U