System on chip/SOC application structure that resets

The utility model discloses a system on chip/SOC application structure that resets, this structure includes external input clock CLK_in, the external input RESET# that resets, external input data signal DATA_in, system on chip/SOC clock CLK_sys, the system on chip/SOC RST_sys that resets, the select...

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Bibliographic Details
Main Author WEI JIANLEI
Format Patent
LanguageChinese
English
Published 02.03.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The utility model discloses a system on chip/SOC application structure that resets, this structure includes external input clock CLK_in, the external input RESET# that resets, external input data signal DATA_in, system on chip/SOC clock CLK_sys, the system on chip/SOC RST_sys that resets, the selected back data output signal DATA_cap of timesharing, timesharing reset control module U01, control module U02 is markd to the phase -locked loop, multiplexing pin function latchs module U03 and the synchronization generation module U04 that resets, timesharing reset control module U01's input is external input clock CLK_in and the external input RESET# that resets, timesharing reset control module U01's output is RST_iner. The utility model discloses having reduced chip fin's quantity when solving the different mode of host computer visit, having avoided the increase of host computer access module and the conflict of chip fin quantity, the pin is through the multiplexing structure of timesharing, has realized the au
Bibliography:Application Number: CN201621397098U