Sacrificial stress-reduction wafer level chip scale packaging structure

• Main Authors: XIA WENBIN, LIAO JIANYA, GU CHENGJIN, WANG GANG, FAN JUN, SHEN JIANSHU, QIAN JINGXIAN, LU MENGZE, HUANG XIAOHUA, WANG YEYE
• Format: Patent
• Language: Chinese; English
• Published: 05.11.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The utility model discloses a wafer level chip scale packaging structure, and is a sacrificial stress-reduction wafer level chip scale packaging structure. According to the packaging structure, first, at least three through holes are machined on a passivation layer in positions corresponding to pins to partly expose the pins, and then, a metal line layer is arranged and solder balls are planted to lead lines to an external circuit. The three through holes of the packaging structure are of a sacrificial structure. Failure of lines in the three through holes is definitely failure of the line(s) in one or two of the holes on the two sides, while the line in the middle hole is intact. Therefore, the crack of the line layer can be effectively reduced, and the tensile stress on the two sides of the pins can be reduced.