In-situ metal barrier deposition of sputter etching on interconnect structure
A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier...
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Main Authors | , , , , , , , , |
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Format | Patent |
Language | English |
Published |
30.03.2005
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern. |
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Bibliography: | Application Number: CN200410032489 |