Automatic redistribution layer via generation

• Main Authors: GARDI RENATOMATULLA, VENKATARAMANI, RAJAGOPALAN, SANTOS WARREN ALEXANDER, MARTINEZ RYAN, SURIEL, DENNIS, GLENN, LOCHANTA
• Format: Patent
• Language: Chinese; English
• Published: 01.03.2024
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A system and method for automatically generating an arrangement of vias within a redistribution layer of a semiconductor package is described. A user defines attributes to be used for automatic via generation in a redistribution layer of a semiconductor package (702). Circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator (704). The automatic via generator uses the attributes, data indicating an RDL netlist of signal routes within the RDL, and RDL mask layout data representing a signal mask of a metal layer within the RDL. The processor generates an arrangement of vias in the RDL based on the attributes and an identification of an overlap region between the metal layers. 描述了一种用于自动生成过孔在半导体封装的再分布层内的布置的系统和方法。用户定义要用于半导体封装的再分布层中的自动过孔生成的属性(702)。由该用户使用的计算设备的处理器的电路执行自动再分布层(RDL)过孔生成器的指令(704)。该自动过孔生成器使用这些属性、指示该RDL内的信号路线的RDL网表的数据以及表示该RDL内的金属层的信号掩模的RDL掩模布局数据。该处理器基于这些属性以及金属层之间的重叠区域的标识来生成过孔在该RDL中的布置。