ESD protection device with isolation structure layout to minimize harmonic distortion
Embodiments of the present disclosure generally relate to an ESD protection device with an isolation structure layout that minimizes harmonic distortion. An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells each extending into the semiconductor...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
30.05.2023
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Online Access | Get full text |
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Abstract | Embodiments of the present disclosure generally relate to an ESD protection device with an isolation structure layout that minimizes harmonic distortion. An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells each extending into the semiconductor body from the upper surface, a plurality of n-type wells each extending into the semiconductor body from the upper surface, a first isolation region including an electrical insulator laterally surrounding the p-type well and extending from the upper surface into the semiconductor body at least as deep as the p-type well, and a second isolation region including an electrical insulator laterally surrounding the n-type well and extending from the upper surface into the semiconductor body at least as deep as the n-type well, wherein the p-type wells and the n-type wells alternate with each other in the first direction, and wherein an isolation area of the first isolation region is larger than an isolation area of the s |
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AbstractList | Embodiments of the present disclosure generally relate to an ESD protection device with an isolation structure layout that minimizes harmonic distortion. An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells each extending into the semiconductor body from the upper surface, a plurality of n-type wells each extending into the semiconductor body from the upper surface, a first isolation region including an electrical insulator laterally surrounding the p-type well and extending from the upper surface into the semiconductor body at least as deep as the p-type well, and a second isolation region including an electrical insulator laterally surrounding the n-type well and extending from the upper surface into the semiconductor body at least as deep as the n-type well, wherein the p-type wells and the n-type wells alternate with each other in the first direction, and wherein an isolation area of the first isolation region is larger than an isolation area of the s |
Author | TELLET EMMANUEL JOOST WILLEMAN |
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Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | 使谐波失真最小化的具有隔离结构布局的ESD保护器件 |
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Notes | Application Number: CN202211503551 |
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Snippet | Embodiments of the present disclosure generally relate to an ESD protection device with an isolation structure layout that minimizes harmonic distortion. An... |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | ESD protection device with isolation structure layout to minimize harmonic distortion |
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