ESD protection device with isolation structure layout to minimize harmonic distortion

• Main Authors: JOOST WILLEMAN, TELLET EMMANUEL
• Format: Patent
• Language: Chinese; English
• Published: 30.05.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments of the present disclosure generally relate to an ESD protection device with an isolation structure layout that minimizes harmonic distortion. An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells each extending into the semiconductor body from the upper surface, a plurality of n-type wells each extending into the semiconductor body from the upper surface, a first isolation region including an electrical insulator laterally surrounding the p-type well and extending from the upper surface into the semiconductor body at least as deep as the p-type well, and a second isolation region including an electrical insulator laterally surrounding the n-type well and extending from the upper surface into the semiconductor body at least as deep as the n-type well, wherein the p-type wells and the n-type wells alternate with each other in the first direction, and wherein an isolation area of the first isolation region is larger than an isolation area of the s