Schmitt trigger circuit with two-input NAND gate logic, method and chip

• Main Authors: XU LU, LU YUAN, LIAO YONGBO, WEI CHAO, YUAN PIGEN, HUANG LETIAN
• Format: Patent
• Language: Chinese; English
• Published: 05.05.2023
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention provides a Schmitt trigger circuit with NAND gate logic, a method and a chip, the Schmitt trigger circuit comprises a first input node A, a first PMOS tube, a first NMOS tube, a second input node B, a Schmitt trigger and an output node Y. One end of the first PMOS tube and one end of the first NMOS tube are connected with the second input node B, and the other end of the first PMOS tube and one end of the second NMOS tube are connected with the output node Y. The first PMOS transistor is connected with the Schmitt trigger and the output node Y at the same time, the first NMOS transistor is connected with the output node Y through the Schmitt trigger, and the first input node A is connected with the output node Y through the Schmitt trigger. The problems that the level conversion response time of a traditional CMOS two-input NAND gate circuit is long, and the competition-risk phenomenon exists are solved. When being used as a Schmitt trigger circuit, the Schmitt trigger circuit has all functions