Parallel multi-channel hardware implementation method based on high-speed hybrid encryption algorithm

• Main Authors: LIU XIN, GUO CHUNLU, WANG LIANG, WANG TIANSHUN
• Format: Patent
• Language: Chinese; English
• Published: 18.10.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

The invention relates to a parallel multi-channel hardware implementation method based on a high-speed hybrid encryption algorithm, which comprises a client, an FPGA (Field Programmable Gate Array), a password module and a main control processor, and adopts the high-speed hybrid encryption algorithm. Compared with the prior art, the encryption algorithm is used in a mixed mode, the defects that a single cryptosystem is not high in safety, too low in encryption rate, inconvenient in key management and the like are overcome, and meanwhile optimization design on hardware implementation is carried out on the algorithm limiting encryption and decryption speed improvement in the system. 本发明涉及一种基于高速混合加密算法的并行多路硬件实现方法，包括：客户端、FPGA、密码模块以及主控处理器，并采用了高速混合的加密算法。与现有技术相比，通过混合使用加密算法避免了单一密码体制安全性不高、加密速率过慢、密钥管理不便等缺点，同时对体系中限制加密、解密速度提升的算法进行硬件实现上的优化设计。