Chip packaging method and packaging structure

• Main Authors: WU JIAMENG, LIAO YONGBO, MA YINGJIANG, LI CHUNYAN
• Format: Patent
• Language: Chinese; English
• Published: 30.09.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a packaging method and a packaging structure of a chip. The method comprises the steps that a base is provided, the base comprises a substrate, a chip structure and a metal layer, the chip structure is located on the first surface of the substrate, the metal layer is located on the second surface of the substrate, and the first surface is opposite to the second surface; forming a first conductive adhesive layer on the surface, far away from the substrate, of the metal layer to obtain a target wafer; and cutting and packaging the target wafer. According to the method, the first conductive adhesive layer is formed on the metal layer on the second surface of the substrate, so that the thickness of the target wafer can be increased, and the stress of the metal layer can be reduced, thereby reducing the risk that the wafer is too thin to cut and crack and the risk that the wafer is easy to break during transportation; thus, the problem that in the prior art, in the wafer cutting and transpor