METHOD FOR ERROR DETECTION AND CORRECTION AND CORRESPONDING SYSTEM AND DEVICE

A method may include, in response to receiving a read request at a memory controller, sending a read command and an address value on a command address bus in synchronization with a clock. In one embodiment, in response to a read command, a burst of uninterrupted read data values is received on at le...

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Bibliographic Details
Main Authors ZITLAW, CHRISTIAN, WHITLEY MARK
Format Patent
LanguageChinese
English
Published 18.03.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method may include, in response to receiving a read request at a memory controller, sending a read command and an address value on a command address bus in synchronization with a clock. In one embodiment, in response to a read command, a burst of uninterrupted read data values is received on at least one parallel data bus, the burst of read data values having a double data rate relative to a clock, and in response to the same read command, an error correction code (ECC) value of the read data value is received, the burst of read data values having a double data rate relative to the clock. The ECC value is not included in a burst of read data values output on a non-ECC input/output (I/O), where the non-ECC I/O is an I/O that is not assigned to the ECC data according to a pre-existing standard organization. Corresponding systems and devices are disclosed. 一种方法可以包括：响应于在存储器控制器处接收到读取请求，在命令地址总线上与时钟同步地发送读取命令和地址值。响应于读取命令，在至少一个并行数据总线上接收不间断的读取数据值的突发，该读取数据值的突发具有相对于时钟的双倍数据速率，以及响应于相同的读取命令而接收读取数据值的纠错码(ECC)值，该ECC值不被包括在非EC
Bibliography:Application Number: CN202080055642