CACHE CONTROL AWARE MEMORY CONTROLLER

• Main Authors: BALAKRISHNAN GANESH, BHARGAVA RAVINDRA N
• Format: Patent
• Language: Chinese; English
• Published: 18.09.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. External system memory is used as a last-level cache and includes one of a variety of types of dynamic random access memory (DRAM). A memory controller generates a tag request and a separate data request based on a same, single received memory request. The sending of the tag request isprioritized over sending the data request. A partial tag comparison is performed during processing of the tag request. If a tag miss is detected for the partial tag comparison, then the data request is cancelled, and the memory request is sent to main memory. If one or more tag hits are detected for the partial tag comparison, then processing of the data request is dependent upon the result of thefull tag comparison. 公开了用于执行计算系统的高效存储器访问的系统、设备和方法。外部系统存储器用作最后层级高速缓存并且包括多种类型的动态随机存取存储器(DRAM)中的一种。存储器控制器基于相同的单个接收到的存储器请求来生成标签请求和单独的数据请求。所述标签请求的发送优先于发送所述数据请求。在所述标签请求的处理期间执行部分标签比较。如果针对所述部分标签比较检测到标签未命中，则取消所述数据请求，并且将所述存储器请求发送到主存储器。