Selectable bit width error correction and detection circuit for single event upset resistant memory

• Main Authors: WANG WENFENG, CHEN LEI, NI JIE, LI XUEWU, ZHEN SHUQI, HE CAI, GUO KUN, SUN HUABO, LIU YAZE, SUN JIANSHUANG
• Format: Patent
• Language: Chinese; English
• Published: 27.03.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; INFORMATION STORAGE; PHYSICS; STATIC STORES

The invention discloses a selectable bit width error correction and detection circuit for a single event upset resistant memory. The selectable bit width error correction and detection circuit comprises an error correction and detection encoding module and an error correction and detection decoding module, the error correction and detection encoding module can perform check code encoding operationon input data with 11-64 bit widths, generates an 8-bit check code for performing error correction and detection on the data, and outputs the 8-bit check code and the input data to the error correction and detection decoding module together; and the error correction, detection and decoding module is used for decoding and checking the data signal, outputting a one-bit error prompt and an error position when a one-bit error exists in the data signal, correcting the error, and outputting a two-bit error prompt when a two-bit error exists in the data signal. According to the invention, a small circuit area can be used; o