STEEP SLOPED VERTICAL TUNNEL FIELD-EFFECT TRANSISTOR

The invention describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrin...

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Bibliographic Details
Main Authors PASSLACK MATTHIAS, RAMVALL PETER
Format Patent
LanguageChinese
English
Published 26.11.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES
NANOTECHNOLOGY
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES
TRANSPORTING
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Summary:The invention describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer. 本揭示内容描述一种垂直穿隧场效晶体管装置，其包括P掺杂的氮化镓纳米线源极/漏极的垂直的P-I-N异质接面结构、本质的InN层，和N掺杂的氮化镓纳米线源极/漏极。高介电常数介电层和金属栅极环绕本质的InN层周围。
Bibliography:Application Number: CN201810818182