Integrated circuit containing DOEs of NCEM-enabled fill cells

• Main Authors: O'SULLIVAN CONOR, MICHAELS KIMON, DOONG KELVIN, STROJWAS ANDRZEJ, KIBARIAN JOHN, STROJWAS MARCIN, BROZEK TOMASZ, LIAO MARCI, LAM STEPHEN, DE INDRANIL, MATSUHASHI HIDEKI, EISENMANN HANS, ROVNER VYACHESLAV, RAUSCHER MARKUS, VALLISHAYEE RAKESH, FISCUS TIMOTHY, CHENG JEREMY, HAIGH JONATHAN, YOKOYAMA NOBUHARU, CIPLICKAS DENNIS, WEILAND LARG, HESS CHRISTOPHER, COMENSOLI SIMONE, TAYLOR CARL, LIN SHENG, LEE SHERRY
• Format: Patent
• Language: Chinese; English
• Published: 04.09.2018
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments ("DOEs"), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s). 晶片、芯片或晶粒，其包含具有被配置为经由非接触电测量("NCEM")获得联机数据的结构的填充单元。这些实现了NCEM的填充单元可以标定/暴露各种开路、短路、泄漏或过度电阻故障模式。这些晶片、芯片或晶粒可以包括实验设计("DOE")，其在至少两个变型中包括多个实现了NCEM的填充单元，全都指向相同故障模式。