Method and system for automatic generation of module-level simulation and code configuration of programmable logic circuit

• Main Authors: YANG HAIGANG, ZHAO HE, HUANG ZHIHONG, DI XINKAI, YIN TAO, TU KAIHUI, XU YU, MAO NING, WEI XING
• Format: Patent
• Language: Chinese; English
• Published: 10.04.2018
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a method for automatic generation of module-level simulation and code configuration of a programmable logic circuit. The method comprises the following steps: analyzing a bottom-layer circuit structure of FPGA, respectively creating configuration addressing models of a bottom-layer circuit and building corresponding module-level code configuration models in combination withsignal connection relations among all layers and all modules of FPGA and SRAM configuration bit information; determining an input port and an output port of a submodule-level circuit through an appointed path in need of simulation and code configuration; determining a path in need of configuration and connection by positioning through the determined input port and the determined output port, finding an SRAM bit in need of configuration and connection according to a module-level code configuration model and outputting an SRAM configuration code stream through an agreed-on output format. With the method, working effici