IP ROUTE CACHING WITH TWO SEARCH STAGES ON PREFIX LENGTH

• Main Authors: GIL LEVY, AMIR ROITSHTEIN, AVIV KFIR, PEDRO REVIRIEGO, SALVATORE PONTARELLI, FIMA KRAVCHIK
• Format: Patent
• Language: Chinese; English
• Published: 29.12.2017
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information. 本申请涉及利用对前缀长度进行两个搜索阶段的IP路由缓存。数据包在网元中被接收。网元具有高速缓冲存储器，其中缓存条目表示被储存在主存储器中的地址的部分。目的地址和缓存条目各自包括二进制数。做出缓存条目的和目的地址的M个最高有效位是相同的第确定。做出缓存条目的和目的地址的附加的M+L个最高有效位是相同的第二确定。路由信息随后被从高速缓冲存储器中检索出来，并且包根据该路由信息进行处理。