Power management for memory accesses in a system-on-chip

• Main Authors: VAZ IRWIN J, BIBIKAR VASUDEV, ABRAHAM PHILIP, KATHURIA MANAN, MACHER STEFAN, ROHIT VERMA R, PARTIWALA SUKETU R
• Format: Patent
• Language: Chinese; English
• Published: 19.04.2017
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Techniques and mechanisms to manage power states for a system-on-chip (SOC). Multiple modules of the SOC include a first module to perform a task including one or more accesses to a memory. In an embodiment, the SOC is transitioned to one of a path-to-memory-available (PMA) power state and a path-to-memory-not-available (PMNA) power state, where the transition is in response to an indication that, of the multiple modules, only the first module is to access the memory during the task. The PMA power state enables data communication between the memory and the first module and prevents data communication between the memory and any other module of the multiple modules. In another embodiment, the PMNA power state prevents data communication between the memory and any of the multiple modules, but allows a low latency transition from the PMNA power state to the PMA power state. 用于管理芯片上系统（SOC）的功率状态的技术和机制。该SOC的多个模块包括第模块，用于执行任务，其包括对存储器的个或多个访问。在实施例中，SOC转变到到存储器路径可用（PMA）功率状态和到存储器路径不可用（PMNA）功率状态中的个，其中该转变响应于在多个模块中仅第模块在任务期间要访