Multi-node current loop full-duplex communication circuit

The invention discloses a multi-node current loop full-duplex communication circuit which comprises first, second and third communication terminals and an intermediate node circuit. The second and third communication terminals are in circuit loop communication with the first communication terminal s...

Full description

Saved in:
Bibliographic Details
Main Authors WANG BENLIANG, WANG YELIU, ZHANG YAN, LIU GONGQING, YIN YUAN, SU JUNGUI, LING YUAN, WANG QIANG, ZHENG HONGCHANG, SHEN ZHULIN
Format Patent
LanguageChinese
English
Published 06.04.2016
Subjects
Online AccessGet full text

Cover

Loading…
Abstract The invention discloses a multi-node current loop full-duplex communication circuit which comprises first, second and third communication terminals and an intermediate node circuit. The second and third communication terminals are in circuit loop communication with the first communication terminal simultaneously via the intermediate node circuit. The intermediate node circuit comprises a power supply circuit, a sending circuit and a reception circuit, and the power supply circuit receives power provided by the second and third communication terminals, and provides working power for the sending and reception circuits according to a power control signal provided by the third communication terminal. When the first communication terminal sends data, the reception circuit receives current signals from the first communication terminal, converts the current signals, and sends the converted current signals to the second and third communication terminals. When the first communication terminal receives data, the sendin
AbstractList The invention discloses a multi-node current loop full-duplex communication circuit which comprises first, second and third communication terminals and an intermediate node circuit. The second and third communication terminals are in circuit loop communication with the first communication terminal simultaneously via the intermediate node circuit. The intermediate node circuit comprises a power supply circuit, a sending circuit and a reception circuit, and the power supply circuit receives power provided by the second and third communication terminals, and provides working power for the sending and reception circuits according to a power control signal provided by the third communication terminal. When the first communication terminal sends data, the reception circuit receives current signals from the first communication terminal, converts the current signals, and sends the converted current signals to the second and third communication terminals. When the first communication terminal receives data, the sendin
Author LING YUAN
SU JUNGUI
WANG YELIU
LIU GONGQING
ZHENG HONGCHANG
SHEN ZHULIN
ZHANG YAN
WANG QIANG
WANG BENLIANG
YIN YUAN
Author_xml – fullname: WANG BENLIANG
– fullname: WANG YELIU
– fullname: ZHANG YAN
– fullname: LIU GONGQING
– fullname: YIN YUAN
– fullname: SU JUNGUI
– fullname: LING YUAN
– fullname: WANG QIANG
– fullname: ZHENG HONGCHANG
– fullname: SHEN ZHULIN
BookMark eNrjYmDJy89L5WSw9C3NKcnUzctPSVVILi0qSs0rUcjJzy9QSCvNydFNKS3ISa1QSM7PzS3Ny0xOLMnMz1NIzixKLs0s4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgamJuaGpmaWjsbEqAEAgJYxAA
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID CN105471569A
GroupedDBID EVB
ID FETCH-epo_espacenet_CN105471569A3
IEDL.DBID EVB
IngestDate Fri Jul 19 16:48:44 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language Chinese
English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_CN105471569A3
Notes Application Number: CN20141463147
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160406&DB=EPODOC&CC=CN&NR=105471569A
ParticipantIDs epo_espacenet_CN105471569A
PublicationCentury 2000
PublicationDate 20160406
PublicationDateYYYYMMDD 2016-04-06
PublicationDate_xml – month: 04
  year: 2016
  text: 20160406
  day: 06
PublicationDecade 2010
PublicationYear 2016
RelatedCompanies ZHUZHOU CSR TIMES ELECTRIC CO., LTD
RelatedCompanies_xml – name: ZHUZHOU CSR TIMES ELECTRIC CO., LTD
Score 3.1461265
Snippet The invention discloses a multi-node current loop full-duplex communication circuit which comprises first, second and third communication terminals and an...
SourceID epo
SourceType Open Access Repository
SubjectTerms ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Title Multi-node current loop full-duplex communication circuit
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160406&DB=EPODOC&locale=&CC=CN&NR=105471569A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NS8MwFH_MKepNp6LzgwjSW1C7NlsPRVy6MgS7IVN2G02ascpoy9ai-Nf7Gju3i95CAo8k5JeX9_F7AbixZeiIjimpjMyQWmgoU9SKDm3JMuZnCWlJnSAbsP6r9TS2xzV4X3FhdJ3QD10cERElEe-5vq-ztRPL07mVy1sRY1f64I9cz6is43uGZ5IZXtftDQfegBucuzwwghd869p4DdvMedyCbXxGt0s09N66JSsl21Qp_gHsDFFakh9C7WvWgD2--nmtAbvPVcAbmxX2lkfgaK4sTdJIEflTVYnM0zQjpQedRkU2V59EbvI9iIwXsojzY7j2eyPepziHye-CJzxYT7d1AvUkTdQpEDENldU2BYJmainU9HbHQXNE4bJZKO7UGTT_ltP8b_Ac9svN0xkp7ALq-aJQl6hsc3Gld-kb0Q-DwA
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NT8IwFH9BNOJNUaP4VROzW6NCV9iBGOkgqDCImYYbWUuJGLItMKLxr_etDuGit6ZNXtqmv76-j98rwJWtAkfWyoqqUTmgDA1lilrRoRWVxvyYVEyZBFmPt1_Y48Ae5OB9yYUxdUI_THFERJRCvCfmvo5XTizX5FbOr-UEu6K7ll93rcw6vuV4JrnlNurNfs_tCUuIuvAs7xnfujZewzZ37jdgE5_Y1RQNzddGykqJ11VKaxe2-igtTPYg9_VWhIJY_rxWhO1uFvDGZoa9-T44hitLw2ikifqpqkSmURST1INOR4t4qj-JWud7EDWZqcUkOYDLVtMXbYpzGP4ueCi81XQrh5APo1AfAZHjQLNqWSJoxkyjprdrDpojGpfNA3mjj6H0t5zSf4MXUGj73c6w8-A9ncBOupEmO4WfQj6ZLfQZKt5Enpsd-wYqOIaz
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Multi-node+current+loop+full-duplex+communication+circuit&rft.inventor=WANG+BENLIANG&rft.inventor=WANG+YELIU&rft.inventor=ZHANG+YAN&rft.inventor=LIU+GONGQING&rft.inventor=YIN+YUAN&rft.inventor=SU+JUNGUI&rft.inventor=LING+YUAN&rft.inventor=WANG+QIANG&rft.inventor=ZHENG+HONGCHANG&rft.inventor=SHEN+ZHULIN&rft.date=2016-04-06&rft.externalDBID=A&rft.externalDocID=CN105471569A