Integrated circuit and method for establishing scanning test framework in integrated circuit

• Main Authors: WEN-HAO HSUEH, SHANG-BIN HUANG, CHONG DAI, JIANGUO REN, FENGGUO GAO
• Format: Patent
• Language: English
• Published: 30.09.2015
• Subjects: MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

The invention discloses an integrated circuit and a method for establishing a scanning test framework in the integrated circuit. The integrated circuit comprises multiple circuit modules. Each circuit module comprises a clock control unit, a first pipeline unit, a serial compression scanning circuit and a second pipeline unit. The clock control unit generates a first scanning clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the first scanning clock. The serial compression scanning circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scanning clock. The first scanning clock of each of the aforementioned circuit modules is independent of the first scanning clocks of other circuit modules so that timing sequence analysis and adjustment difficulty and cost can be reduced.