High performance SOI non-junction transistor of non-monolithic substrate insulation layer thickness

• Main Authors: JIN XIAOSHI, LIU XI, WU MEILE, CHUAI RONGYAN
• Format: Patent
• Language: English
• Published: 22.04.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to a high performance SOI non-junction transistor of a non-monolithic substrate insulation layer thickness. An employed SOI wafer insulation layer thickness is not single-valued in the unit length of a transistor. By properly increasing the thickness of the parts, near a source region and a drain region, of an SOI wafer insulation layer, the resistance of the source region and the drain region is greatly reduced, and the positive onset property of a component is greatly improved. By properly decreasing the thickness of the parts, under corresponding gate electrodes, of the SOI wafer insulation layer, local enhancement on the voltage regulating effect of a substrate can be achieved, the substrate voltage bias needed for auxiliary grid control can be lowered, and voltage control over the lower part of the substrate can be achieved. By optimizing the relative positions and sizes of the thicker part and the thinner part of the insulation layer of the SOI wafer, the reverse leakage current caused by band-to-band tunneling around the junctions of a component channel and drain electrodes when reversal of biasing of the gate electrodes occurs is effectively reduced. Therefore, the high performance SOI non-junction transistor is suitable for widespread application.