Chip package
A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A rec...
Saved in:
| Main Authors | , , , |
|---|---|
| Format | Patent |
| Language | English |
| Published |
24.06.2015
|
| Subjects | |
| Online Access | Get full text |
Cover
Loading…
| Abstract | A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. |
|---|---|
| AbstractList | A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. |
| Author | HSU CHANG-SHENG LEE PO-HAN LIN CHIA-SHENG TSAI CHIA-LUN |
| Author_xml | – fullname: LIN CHIA-SHENG – fullname: TSAI CHIA-LUN – fullname: HSU CHANG-SHENG – fullname: LEE PO-HAN |
| BookMark | eNrjYmDJy89L5WTgcc7ILFAoSEzOTkxP5WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcVAVal5qSXxzn6GBkaGpuYmlkZOTsZEKQIA5MMfpw |
| ContentType | Patent |
| DBID | EVB |
| DatabaseName | esp@cenet |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Medicine Chemistry Sciences |
| ExternalDocumentID | CN102157492BB |
| GroupedDBID | EVB |
| ID | FETCH-epo_espacenet_CN102157492BB3 |
| IEDL.DBID | EVB |
| IngestDate | Fri Jul 19 15:06:15 EDT 2024 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-epo_espacenet_CN102157492BB3 |
| Notes | Application Number: CN201110020991 |
| OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150624&DB=EPODOC&CC=CN&NR=102157492B |
| ParticipantIDs | epo_espacenet_CN102157492BB |
| PublicationCentury | 2000 |
| PublicationDate | 20150624 |
| PublicationDateYYYYMMDD | 2015-06-24 |
| PublicationDate_xml | – month: 06 year: 2015 text: 20150624 day: 24 |
| PublicationDecade | 2010 |
| PublicationYear | 2015 |
| RelatedCompanies | XINTEC INC |
| RelatedCompanies_xml | – name: XINTEC INC |
| Score | 2.9953094 |
| Snippet | A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing... |
| SourceID | epo |
| SourceType | Open Access Repository |
| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| Title | Chip package |
| URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150624&DB=EPODOC&locale=&CC=CN&NR=102157492B |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSUkF1nuGyUm6BommlromZmlGupaJwLScZpZiaWZqnJKcCL61xNfPzCPUxCvCNIKJIQu2FwZ8Tmg5-HBEYI5KBub3EnB5XYAYxHIBr60s1k_KBArl27uF2LqoQXvHoOPyjEzUXJxsXQP8Xfyd1ZydbZ391PyCbEE3WJuam1gaOTEzsIKa0aBz9l3DnEC7UgqQqxQ3QQa2AKBpeSVCDEypecIMnM6wm9eEGTh8oRPeQCY07xWLMPA4Z2QWKABdmw0sAkQZlNxcQ5w9dIHGxsP9EO_sh3CBk7EYAwuwc58qwaBgkGiRnGaRbGqWZGliYmKcmGSemGJikGQKzBdAhqmpJIM0HoOk8MpKM3CBggS0sMnIRIaBpaSoNFUWWIWWJMmB_Q4A7gJy9A |
| link.rule.ids | 230,309,786,891,25594,76903 |
| linkProvider | European Patent Office |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFCe-6FTU-TFE-lbs2qRdH4rQdKXq2g2psreS9AOnMIur-O97DZ3zaW9HAsflyO-OS-4D4DbL0e8NUqFqnNoqMQtdtTne5cLMbJMaWcrl1JIwMoMX8jijsxa8r2phZJ_QH9kcERGVIt4raa_L9SOWJ3Mrl3dijkuf937seEoTHdft8nSieK4zmk68CVMYc1ikRM9OPcGaWsTW3S3YtjAklKHSq1tXpZT_XYp_ADtT5LaoDqGVL7rQYavJa13YDZsPbyQb7C2PYJ-9zcs-SvuBJuAYbvxRzAIV2SZ_Z0hYtJbANU6gjcF9fgp9jQ_TYphSU9iEEIMLi2dEExRxgQSlZ9DbwOh84-41dII4HCfjh-ipB3u1euokJ51cQLv6-s4v0Z1W4krq4RdyeHXe |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Chip+package&rft.inventor=LIN+CHIA-SHENG&rft.inventor=TSAI+CHIA-LUN&rft.inventor=HSU+CHANG-SHENG&rft.inventor=LEE+PO-HAN&rft.date=2015-06-24&rft.externalDBID=B&rft.externalDocID=CN102157492BB |