Chip package

A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A rec...

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Bibliographic Details
Main Authors LIN CHIA-SHENG, TSAI CHIA-LUN, HSU CHANG-SHENG, LEE PO-HAN
Format Patent
LanguageEnglish
Published 24.06.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.
Bibliography:Application Number: CN201110020991